The present invention relates to computer apparatus. More particularly, it relates to power sequencing control for the memory of a computer.
The memory units in computer apparatus are energized by power sources representing different energy or voltage levels. Because of the intricacies of the memory units, these several power sources may not be simultaneously applied to the memory units nor may they be simultaneously removed from the memory units. Rather, the power units must be applied in a predetermined sequence and after predetermined delays. Similarly, the removal of power from the memory unit must also follow a comparable sequence. Upon the detection of certain faults in the various power sources, the power must be removed from the memory units again in a predetermined sequence with predetermined delays therein. Heretofore, such sequencing has been accomplished through dedicated and discrete circuitry for each of the power signal lines with discrete RC networks constituting individual delay means. Such structures were characterized by being relatively expensive both in the number of parts and in the time consumed in assembling such parts, as well as being subject to failure in any of a large number of parts.